Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. The advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
Complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) are employed in almost every electronic circuit application including, for example, signal processing, computing, and wireless communications. As transistor devices continue to scale, a reduction in FET gate size has also led to a decrease in thickness of the SOI layer in order to control short channel effects. In fact, the so-called extremely thin SOI or ETSOI devices can have SOI thickness on the order of about 10 nanometers (nm) or less.
Within the technology of complementary metal oxide semiconductor (CMOS) transistors, dual stress liners have been used to improve both N-type and P-type transistor performance. The carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. An increase in the performance of an n-type field effect transistor NFET can be achieved by applying a tensile longitudinal stress of the conduction channel of the NFET. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive longitudinal stress to the conduction channel of the PFET.
On SOI wafers, stress effect from the buried on oxide layer (BOX) is usually not an issue since the stress will drop to a negligible level at the channel to the silicon thickness on the BOX layer. However, on ETSOI wafers, the stress effect from the BOX can have an impact on the transistors on top due to the extremely thin silicon layer. This allows for stress engineering on buried insulators to enhance CMOS performance.
The invention uses existing silicon-on-nothing (SON) techniques to create an ETSOI wafer structure with dual stress buried insulators. SON have air-gaps under channel regions. With the air-gaps, the short channel effect of the SON is improved, and leakage currents can be reduced. One conventional process includes forming a silicon germanium (SiGe) layer on a silicon substrate, forming a silicon layer on the SiGe layer, forming a gate over the silicon layer, forming source and drain recesses, and etching the silicon germanium layer to form the air-gap. This can be accomplished by a variety of embodiments as will be disclosed further.